|
enum | ESpiType {
TYPE_COMMAND_TYPE
, TYPE_CAPS_ADDR
, TYPE_COMMAND_DATA_8
, TYPE_COMMAND_DATA_32
,
TYPE_COMMAND_CRC_GOOD
, TYPE_COMMAND_CRC_BAD
, TYPE_RESPONSE_OP
, TYPE_RESPONSE_STATUS
,
TYPE_RESPONSE_DATA_32
, TYPE_RESPONSE_CRC_GOOD
, TYPE_RESPONSE_CRC_BAD
, TYPE_VWIRE_COUNT
,
TYPE_VWIRE_INDEX
, TYPE_VWIRE_DATA
, TYPE_GENERAL_CAPS_RD
, TYPE_GENERAL_CAPS_WR
,
TYPE_CH0_CAPS_RD
, TYPE_CH0_CAPS_WR
, TYPE_CH1_CAPS_RD
, TYPE_CH1_CAPS_WR
,
TYPE_CH2_CAPS_RD
, TYPE_CH2_CAPS_WR
, TYPE_REQUEST_TAG
, TYPE_REQUEST_LEN
,
TYPE_FLASH_REQUEST_TYPE
, TYPE_FLASH_REQUEST_ADDR
, TYPE_FLASH_REQUEST_DATA
, TYPE_SMBUS_REQUEST_TYPE
,
TYPE_SMBUS_REQUEST_ADDR
, TYPE_SMBUS_REQUEST_DATA
, TYPE_IO_ADDR
, TYPE_IO_DATA
,
TYPE_WAIT
, TYPE_COMPLETION_TYPE
, TYPE_COMPLETION_DATA
, TYPE_ERROR
} |
|
enum | ESpiCommand {
COMMAND_PUT_PC = 0x00
, COMMAND_GET_PC = 0x01
, COMMAND_PUT_NP = 0x02
, COMMAND_GET_NP = 0x03
,
COMMAND_PUT_OOB = 0x06
, COMMAND_GET_OOB = 0x07
, COMMAND_PUT_FLASH_C = 0x08
, COMMAND_GET_FLASH_NP = 0x09
,
COMMAND_PUT_IORD_SHORT_x1 = 0x40
, COMMAND_PUT_IORD_SHORT_x2 = 0x41
, COMMAND_PUT_IORD_SHORT_x4 = 0x43
, COMMAND_PUT_IOWR_SHORT_x1 = 0x44
,
COMMAND_PUT_IOWR_SHORT_x2 = 0x45
, COMMAND_PUT_IOWR_SHORT_x4 = 0x47
, COMMAND_PUT_MEMRD32_SHORT_x1 = 0x48
, COMMAND_PUT_MEMRD32_SHORT_x2 = 0x49
,
COMMAND_PUT_MEMRD32_SHORT_x4 = 0x4b
, COMMAND_PUT_MEMWR32_SHORT_x1 = 0x4c
, COMMAND_PUT_MEMWR32_SHORT_x2 = 0x4d
, COMMAND_PUT_MEMWR32_SHORT_x4 = 0x4f
,
COMMAND_PUT_VWIRE = 0x04
, COMMAND_GET_VWIRE = 0x05
, COMMAND_GET_STATUS = 0x25
, COMMAND_SET_CONFIGURATION = 0x22
,
COMMAND_GET_CONFIGURATION = 0x21
, COMMAND_RESET = 0xff
, COMMAND_NONE = 0x100
} |
|
enum | ESpiResponse {
RESPONSE_DEFER = 0x1
, RESPONSE_NONFATAL_ERROR = 0x2
, RESPONSE_FATAL_ERROR = 0x3
, RESPONSE_ACCEPT = 0x8
,
RESPONSE_NONE = 0xf
} |
|
enum | ESpiCompletion { COMPLETION_NONE = 0
, COMPLETION_PERIPHERAL = 1
, COMPLETION_VWIRE = 2
, COMPLETION_FLASH = 3
} |
|
enum | ESpiCycleType {
CYCLE_READ = 0
, CYCLE_WRITE = 1
, CYCLE_ERASE = 2
, CYCLE_SMBUS = 0x21
,
CYCLE_SUCCESS_NODATA = 0x06
, CYCLE_SUCCESS_DATA_MIDDLE = 0x09
, CYCLE_SUCCESS_DATA_FIRST = 0x0b
, CYCLE_SUCCESS_DATA_LAST = 0x0d
,
CYCLE_SUCCESS_DATA_ONLY = 0x0f
, CYCLE_FAIL_LAST = 0x08
, CYCLE_FAIL_ONLY = 0x0e
} |
|